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CMOS 220 MHz True-Color Graphics Triple 10-Bit Video RAM-DAC ADV7152
APPLICATIONS High Resolution, True Color Graphics Professional Color Prepress Imaging GENERAL DESCRIPTION
FEATURES 220 MHz, 24-Bit (30-Bit Gamma Corrected) True Color Triple 10-Bit "Gamma Correcting" D/A Converters Triple 256 10 (256 30) Color Palette RAM On-Chip Clock Control Circuit Palette Priority Select Registers RS-343A/RS-170 Compatible Analog Outputs TTL Compatible Digital Inputs Standard MPU l/O Interface 10-Bit Parallel Structure 8+2 Byte Structure Programmable Pixel Port: 24-Bit and 8-Bit (Pseudo) Pixel Data Serializer Multiplexed Pixel Input Ports; 1:1, 2:1 +5 V CMOS Monolithic Construction 100-Lead Plastic Quad Flatpack (QFP) Thermally Enhanced to Achieve JC < 1.0 C/W
The ADV7152 (ADV(R)) is a complete analog output, Video RAM-DAC on a single CMOS monolithic chip. The part is specifically designed for use in high performance, color graphics workstations. The ADV7152 integrates a number of graphic functions onto one device allowing 24-bit direct True-Color operation at the maximum screen update rate of 220 MHz. The ADV7152 implements 30-bit True Color in 24-bit frame buffer designs. The part also supports other modes, including 15-bit True Color and 8-bit Pseudo or Indexed Color. Either the Red, Green or Blue input pixel ports can be used for Pseudo Color. The device consists of three, high speed, 10-bit, video D/A converters (RGB), three 256 10 (one 256 30) color look-up tables, palette priority selects, a pixel input data multiplexer/ serializer and a clock generator/divider circuit. The ADV7152 implements 1:1 and 2:1 pixel data multiplexing. The onboard palette priority select inputs enable multiple palette devices to be connected together for use in multipalette and window (Continued on page 10)
MODES OF OPERATION 24-Bit True Color (30-Bit Gamma Corrected) @ 220 MHz @ 170 MHz @ 135 MHz @ 110 MHz @ 85 MHz ADV is a registered trademark of Analog Devices, Inc. 8-Bit Pseudo Color 15-Bit True Color FUNCTIONAL BLOCK DIAGRAM
VAA 256-COLOR/GAMMA PALETTE RAM RED 256 x 10 P I X E L P O R T 48 MUX 2:1 8 8 8 GREEN 256 x 10 BLUE 256 x 10 4 2 10 10-BIT GREEN DAC 10-BIT BLUE DAC SYNC OUTPUT CONTROL REGISTERS CLOCK CONTROL LOADIN LOADOUT PRGCKOUT SCKIN SCKOUT SYNC BLANK MPU PORT CLOCK CLOCK ECL TO CMOS CE R/W C0 10 (8+2) C1 D9 - D0 GND
CLOCK DIVIDE & SYNCHRONIZATION CIRCUIT /32, /16, /8, /4, /2 PIXEL MASK REGISTER TEST REGISTERS MODE REGISTER (MR1) ID REGISTER COMMAND REGISTERS (CR1-CR3) REVISION REGISTER
ADV7152
10 10-BIT RED DAC IOR IOR IOG IOG IOB IOB IPLL SYNCOUT VREF RSET COMP
24 RED (R0-R7), GREEN (G0-G7), BLUE (B0-B7) COLOR DATA A
24 B
10
PALETTE SELECTS (PS0, PS1)
4
MUX 2:1
DATA TO PALETTES 30
RED REGISTER
VOLTAGE REFERENCE CIRCUIT COLOR REGISTERS
GREEN REGISTER BLUE REGISTER
ADDRESS REGISTER ADDR (A0--A15)
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
(VAA1 = +5 V; VREF = +1.235 V; RSET = 280 CL = 10 pF); IOR, IOG, IOB = GND. All specifications TMIN to TMAX2 unless otherwise noted.)
Parameter STATIC PERFORMANCE Resolution (Each DAC) Accuracy (Each DAC) Integral Nonlinearity Differential Nonlinearity Gray Scale Error Coding DIGITAL INPUTS (Excluding CLOCK, CLOCK) Input High Voltage, V INH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN CLOCK INPUTS (CLOCK, CLOCK) Input High Voltage, V INH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN DIGITAL OUTPUTS Output High Voltage, V OH Output Low Voltage, V OL Floating-State Leakage Current Floating-State Output Capacitance ANALOG OUTPUTS Gray Scale Current Range Output Current White Level Relative to Blank White Level Relative to Black Black Level Relative to Blank Blank Level on IOR, IOB Blank Level on IOG Sync Level on IOG LSB Size DAC-to-DAC Matching Output Compliance, V OC Output Impedance, R OUT Output Capacitance, C OUT VOLTAGE REFERENCE Voltage Reference Range, V REF Input Current, I VREF POWER REQUIREMENTS VAA IAA3 IAA IAA IAA IAA Power Supply Rejection Ratio DYNAMIC PERFORMANCE Clock and Data Feedthrough 4, 5 All Versions 10 1 1 5 Unit Bits LSB max LSB max % Gray Scale max Binary V min V max A max pF typ V min V max A max pF typ V min V max A max pF typ mA min/max mA min/max mA min/max mA min/max A min mA min/max A min/max A typ % max V min/V max k typ pF max V min/V max A typ V nom mA max mA max mA max mA max mA max %/% max dB typ
ADV7152-SPECIFICATIONS
. IOR, IOG, IOB (RL = 37.5
Test Conditions/Comments
,
Guaranteed Monotonic
2 0.8 10 10 VAA - 1.0 VAA - 1.6 10 10 2.4 0.4 20 20 15/22 17.69/20.40 16.74/18.50 0.95/1.90 0/50 6.29/8.96 0/50 17.22 3 0/+1.4 100 30 1.14/1.26 +5 5 400 370 350 330 315 0.5 -30
VIN = 0.4 V or 2.4 V
VIN = 0.4 V or 2.4 V
ISOURCE = 400 A ISINK = 3.2 mA
Typically 19.05 mA Typically 17.62 mA Typically 1.44 mA Typically 5 A Typically 7.62 mA Typically 5 A Typically 1%
IOUT = 0 mA VREF = 1.235 V for Specified Performance
220 MHz Parts 170 MHz Parts 135 MHz Parts 110 MHz Parts 85 MHz Parts Typically 0.12%/%, COMP = 0.1 F
Glitch Impulse DAC-to-DAC Crosstalk6
50 -23
pV secs typ dB typ
NOTES 1 5% for all versions. 2 Temperature range (T MIN to TMAX): 0C to +70C; TJ (Silicon Junction Temperature) 100C. 3 Pixel Port is continuously clocked with data corresponding to a linear ramp. T J = 100C. 4 Clock and data feedthrough is a function of the amount of overshoot and undershoot on the digital inputs. Glitch impulse includes clock and data feedthrough. 5 TTL input values are 0 to 3 volts, with input rise/fall times 3 ns, measured the 10% and 90% points. Timing reference points at 50% for inputs and outputs. 6 DAC-to-DAC crosstalk is measured by holding one DAC high while the other two are making low-to-high and high-to-low transitions. Specifications subject to change without notice.
-2-
REV. B
ADV7152 TIMING CHARACTERISTICS1
Parameter 220 MHz Version
(VAA2 = +5 V; VREF = +1.235 V; RSET = 280 IOR, IOG, I0B = GND. All specifications TMIN to TMAX3 unless otherwise noted.)
170 MHz Version 135 MHz Version 110 MHz Version 85 MHz Version
. IOR, IOG, IOB (RL = 37.5
, CL = 10 pF);
CLOCK CONTROL AND PIXEL PORT 4 Units Conditions/Comments
fCLOCK t1 t2 t3 t4 fLOADIN 1:1 Multiplexing 2:1 Multiplexing t5 1:1 Multiplexing 2:1 Multiplexing t6 1:1 Multiplexing 2:1 Multiplexing t7 1:1 Multiplexing 2:1 Multiplexing t8 t9 t10 -t115 tPD6 1:1 Multiplexing 2:1 Multiplexing t12 t13 t14 t15
ANALOG OUTPUTS7
220 4.55 2 2 10 110 110 9.1 9.1 4 4 4 4 0 5 0 -5 5 6 10 5 5 1
170 5.88 2.5 2.5 10 110 85 9.1 11.76 4 5 4 5 0 5 0 -5 5 6 10 5 5 1
135 7.4 3 3.2 10 110 67.5 9.1 14.8 4 6 4 6 0 5 0 -5 5 6 10 5 5 1
110 9.1 4 4 10 110 55 9.1 18.18 4 8 4 8 0 5 0 -5 5 6 10 5 5 1
85 11.77 4 4 10 85 42.5 11.76 23.53 4 9 4 9 0 5 0 -5 5 6 10 5 5 1
MHz max ns min ns min ns min ns max MHz max MHz max
Pixel CLOCK Rate Pixel CLOCK Cycle Time Pixel CLOCK High Time Pixel CLOCK Low Time Pixel CLOCK to LOADOUT Delay LOADIN Clocking Rate
LOADIN Cycle Time ns min ns min LOADIN High Time ns min ns min LOADIN Low Time ns min ns min ns min ns min ns min ns max CLOCKs CLOCKs ns max ns max ns min ns min
Pixel Data Setup Time Pixel Data Hold Time LOADOUT to LOADIN Delay LOADOUT to LOADIN Delay Pipeline Delay (1 x CLOCK = t1) Pixel CLOCK to PRGCKOUT Delay SCKIN to SCKOUT Delay BLANK to SCKIN Setup Time BLANK to SCKIN Hold Time
Parameter
t16 t17 t18 tSK
220 MHz 170 MHz 135 MHz 110 MHz 85 MHz Version Version Version Version Version Units
15 1 15 2 0 15 1 15 2 0 15 1 15 2 0 15 1 15 2 0 15 1 15 2 0 ns typ ns typ ns typ ns max ns typ
Conditions/Comments
Analog Output Delay Analog Output Rise/Fall Time Analog Output Transition Time Analog Output Skew (IOR, IOG, IOB)
MPU PORTS8, 9
Parameter t19 t20 t21 t22 t238 t249 t259 t26 t27
220 MHz 170 MHz 135 MHz 110 MHz 85 MHz Version Version Version Version Version Units 3 10 45 25 5 45 20 5 20 5 3 10 45 25 5 45 20 5 20 5 3 10 45 25 5 45 20 5 20 5 3 10 45 25 5 45 20 5 20 5 3 10 45 25 5 45 20 5 20 5 ns min ns min ns min ns min ns min ns max ns max ns min ns min ns min
Conditions/Comments R/W, C0, C1 to CE Setup Time R/W, C0, C1 to CE Hold Time CE Low Time CE High Time CE Asserted to Databus Driven CE Asserted to Data Valid CE Disabled to Databus Three-Stated Write Data (D0-D9) Setup Time Write Data (D0-D9) Hold Time
REV. B
-3-
ADV7152
NOTES 1 TTL input values are 0 to 3 volts, with input rise/fall times 3 ns, measured between the 10% and 90% points. ECL inputs (CLOCK, CLOCK) are VAA-0.8 V to V AA-1.8 V, with input rise/fall times 2 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs. Analog output load 10 pF. Databus (D0-D9) loaded as shown in Figure 1. Digital output load for LOADOUT, PRGCKOUT, SCKOUT, I PLL and SYNCOUT 30 pF. 2 5% for all versions. 3 Temperature range (T MIN to TMAX): 0C to +70C; TJ (Silicon Junction Temperature) 100C. 4 Pixel Port consists of the following inputs: Pixel Inputs: RED [A, B]; GREEN [A, B]; BLUE [A, B], Palette Selects: PS0 [A, B]; PS1 [A, B]; Pixel Controls: SYNC, BLANK; Clock Inputs: CLOCK, CLOCK, LOADIN, SCKIN; Clock Outputs: LOADOUT, PRGCKOUT, SCKOUT. 5 is the LOADOUT Cycle Time and is a function of the Pixel CLOCK Rate and the Multiplexing Mode: 1:1 multiplexing; = CLOCK = t1 ns; 2:1 multiplexing, = CLOCK x 2 = 2 x t1 ns. 6 These fixed values for Pipeline Delay are valid under conditions where t 10 and -t11 are met. If either t10 or -t11 are not met, the part will operate but the Pipeline Delay is increased by 2 clock cycles for 2:1 mode after calibration cycle is performed. 7 Output delay measured from the 50% point of the rising edge of CLOCK to the 50% point of full-scale transition. Output rise/fall time measured between the 10% and 90% points of full-scale transition. Settling time measured from the 50% point of full-scale transition to the output remaining within 1 LSB. (Settling time does not include clock and data feedthrough.) 8 t23 and t24 are measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.4 V or 2.4 V. 9 t25 is derived from the measured time taken by the data outputs to change by 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated back to remove the effects of charging the 100 pF capacitor. This means that the time, t 25, quoted in the Timing Characteristics is the true value for the device and as such is independent of external databus loading capacitances. Specifications subject to change without notice.
ISINK
TO OUTPUT PIN
+2.1V 100pF
ISOURCE
Figure 1. Load Circuit for Databus Access and Relinquish Times
t2 t1
CLOCK
t3
CLOCK
t4
LOADOUT (1:1 MULTIPLEXING)
LOADOUT (2:1 MULTIPLEXING)
Figure 2. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK)
t5
LOADIN
t6
t7
t8
PIXEL INPUT DATA*
VALID DATA
t9
VALID DATA VALID DATA
*INCLUDES PIXEL DATA (R0-R7, G0-G7, B0-B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK
Figure 3. LOADIN vs. Pixel Input Data
-4-
REV. B
ADV7152
CLOCK
t10
LOADOUT
LOADIN
PIXEL INPUT DATA*
AN BN
DIGITAL
AN+1 BN+1
AN+2 BN+2
INPUT TO
ANALOG
OUTPUT
PIPELINE
ANALOG OUTPUT DATA
IOR, IOR IOG, IOG IOB, IOB IPLL , SYNCOUT tPD
AN-1
BN-1
AN
BN
AN+1
BN+1
AN+2
BN+2
*INCLUDES PIXEL DATA (R0-R7, G0-G7, B0-B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK
Figure 4. Pixel Input to Analog Output Pipeline with Minimum LOADOUT to LOADIN Delay (2:1 Multiplex Mode)
CLOCK
- t11
LOADOUT
LOADIN
PIXEL INPUT DATA*
AN BN
DIGIT AL IN PUT T
AN+1 BN+1
AN+2BN+2
O ANA
LOG O
UTPU
T PIPE
LINE
ANALOG OUTPUT DATA
IOR, IOR IOG, IOG IOB, IOB IPLL , SYNCOUT
AN-1
BN-1
AN
BN
AN+1
BN+1
AN+2
BN+2
tPD
*INCLUDES PIXEL DATA (R0-R7, G0-G7, B0-B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK
Figure 5. Pixel Input to Analog Output Pipeline with Maximum LOADOUT to LOADIN Delay (2:1 Multiplex Mode)
CLOCK
PRGCKOUT (CLOCK/4)
PRGCKOUT (CLOCK/8)
PRGCKOUT (CLOCK/16)
PRGCKOUT (CLOCK/32)
t12
*INLCUDES PIXEL DATA (R0-R7, G0-G7, B0-B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK
Figure 6. Pixel Clock Input vs. Programmable Clock Output (PRGCKOUT)
REV. B
-5-
ADV7152
t13
SCKIN
t14
t15
BLANKING PERIOD BLANK
SCKOUT
END OF SCAN LINE (N)
START OF SCAN LINE (N+1)
*INCLUDES PIXEL DATA (R0-R7, G0-G7, B0-B7); PALETTE SELECT INPUTS (PS0-PS1); SYNC; BLANK
Figure 7. Video Data Shift Clock Input (SCKIN) & BLANK vs. Video Data Shift Clock Output (SCKOUT)
CLOCK
t16
t18
WHITE LEVEL 90 %
ANALOG OUTPUTS
IOR, IOR IOG, IOG IOB, IOB IPLL , SYNCOUT
50 %
FULL SCALE TRANSITION
10 % BLACK LEVEL
t17
NOTE: THIS DIAGRAM IS NOT TO SCALE. FOR THE PURPOSES OF CLARITY, THE ANALOG OUTPUT WAVEFORM IS MAGNIFIED IN TIME AND AMPLITUDE W.R.T. THE CLOCK WAVEFORM. IPLL AND SYNCOUT ARE DIGITAL OUTPUT SIGNALS. t 16 IS THE ONLY RELEVANT OUTPUT TIMING SPECIFICATION FOR IPLL AND SYNCOUT.
Figure 8. Analog Output Response vs. CLOCK
t19
R/W, C0, C1
t20
VALID CONTROL DATA
t21
CE
t22 t24
D0-D9 (READ MODE)
t23
R/W = 1
t25
D0-D9 (WRITE MODE)
R/W = 0
t26
t27
Figure 9. Microprocessor Port (MPU) Interface Timing
-6-
REV. B
ADV7152 RECOMMENDED OPERATING CONDITIONS
Parameter Power Supply Ambient Operating Temperature Reference Voltage Output Load Symbol VAA TA VREF RL Min 4.75 0 1.14 Typ 5.00 1.235 37.5 Max 5.25 +70 1.26 Units Volts C Volts
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADV7152 features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality. ABSOLUTE MAXIMUM RATINGS 1
WARNING!
ESD SENSITIVE DEVICE
PIN ASSIGNMENTS
VAA to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 V Voltage on Any Digital Pin . . . . GND - 0.5 V to VAA + 0.5 V Ambient Operating Temperature (TA) . . . . . -55C to +125C Storage Temperature (TS) . . . . . . . . . . . . . . -65C to +150C Junction Temperature (TJ) . . . . . . . . . . . . . . . . . . . . +150C Lead Temperature (Soldering, 10 secs) . . . . . . . . . . . +260C Vapor Phase Soldering (1 minute) . . . . . . . . . . . . . . . +220C Analog Outputs to GND2 . . . . . . . . . . . . . GND - 0.5 to VAA
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those listed in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Analog Output Short Circuit to any Power Supply or Common can be of an indefinite duration.
Pin No. Mnemonic 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 SYNC BLANK R0A R0B GND R1A R1B R2A R2B R3A R3B R4A R4B R5A R5B R6A R6B R7A R7B G0A G0B G1A G1B G2A G2B NC G3A G3B G4A G4B G5A G5B CLOCK CLOCK LOADIN LOADOUT VAA VAA PRGCKOUT SCKIN
Pin No. 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
Mnemonic SCKOUT SYNCOUT GND GND GND GND G6A G6B G7A G7B PS0A PS0B PS1A PS1B B0A B0B B1A B1B B2A B2B B3A B3B B4A B4B B5A B5B B6A B6B B7A B7B CE R/W C0 C1 D0 D1 D2 GND D3 D4
Pin No. Mnemonic 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 D5 VAA D6 D7 D8 D9 GND GND IOB IOR IOG IOB IOG VAA IPLL IOR COMP VREF RSET VAA
ORDERING GUIDE1, 2, 3
Speed 220 MHz 170 MHz 135 MHz ADV7152LS220 ADV7152LS170 ADV7152LS135 110 MHz ADV7152LS110 85 MHz ADV7152LS85
NOTES 1 ADV7152 is packaged in a 100-pin plastic quad flatpack, QFP. 2 All devices are specified for 0C to +70C operation. 3 Contact sales office for latest information on package design.
100-Lead QFP Configuration
80 ROW C 51
81
50
ROW D
Top View (Not to Scale)
PIN NO. 1 IDENTIFIER 100 ROW A 31
1
30
ROW B
ADV7152 QFP
NC = NO CONNECT.
REV. B
-7-
ADV7152
PIN FUNCTION DESCRIPTION
Mnemonic RED (R0A . . . R0B-R7A . . . R7B), GREEN (G0A . . . G0B-G7A. . . G7B), BLUE (B0A . . . B0B-B7A . . . B7B) PS0A . . . PS0B, PS1A . . . PS1B
Function Pixel Port (TTL Compatible Inputs). 48 pixel select inputs, with 8 bits each for Red, 8 bits for Green and 8 bits for Blue. Each bit is multiplexed [A-B] 2:1 or 1:1. It can be configured for 24-Bit True-Color Data, 8-Bit Pseudo-Color Data and 15-Bit True-Color Data formats. Pixel Data is latched into the device on the rising edge of LOADIN. Palette Priority Selects (TTL Compatible Inputs): These pixel port select inputs determine whether or not the device's pixel data port is selected on a pixel by pixel basis. The palette selects allow switching between multiple palette devices. The device can be preprogrammed to completely shut off the DAC analog outputs. If the values of PS0 and PS1 match the values programmed into bits MR16 and MR17 of the Mode Register, then the device is selected. Each bit is multiplexed [A-B] 2:1 or 1:1. PS0 and PS1 are latched into the device on the rising edge of LOADIN. Pixel Data Load Input (TTL Compatible Input). This input latches the multiplexed pixel data, including PS0-PS1, BLANK and SYNC into the device. Pixel Data Load Output (TTL Compatible Output). This output control signal runs at a divided down frequency of the pixel CLOCK input. Its frequency is a function of the multiplex rate. It can be used to directly or indirectly drive LOADIN fLOADOUT = fCLOCK/M where (M = 1 for 1:1 Multiplex Mode) where (M = 2 for 2:1 Multiplex Mode).
LOADIN LOADOUT
PRGCKOUT
Programmable Clock Output (TTL Compatible Output). This output control signal runs at a divided down frequency of the pixel CLOCK input. Its frequency is user programmable and is determined by bits CR30 and CR31 of Command Register 3 fPRGCKOUT = fCLOCK/N where N = 4, 8, 16 and 32.
SCKIN
Video Shift Clock Input (TTL Compatible Input). The signal on this input is internally gated synchronously with the BLANK signal. The resultant output, SCKOUT, is a video clocking signal that is stopped during video blanking periods. Video Shift Clock Output (TTL Compatible Output). This output is a synchronously gated version of SCKIN and BLANK. SCKOUT, is a video clocking signal that is stopped during video blanking periods. Clock Inputs (ECL Compatible Inputs). These differential clock inputs are designed to be driven by ECL logic levels configured for single supply (+5 V) operation. The clock rate is normally the pixel clock rate of the system. Composite Blank (TTL Compatible Input). This video control signal drives the analog outputs to the blanking level. Composite-Sync Input (TTL Compatible Input). This video control signal drives the IOG analog output to the SYNC level. It is only asserted during the blanking period. CR22 in Command Register 2 must be set if SYNC is to be decoded onto the analog output, otherwise the SYNC input is ignored. Composite SYNC O/P (TTL Compatible Output). This video output is a delayed version of SYNC. The delay corresponds to the number of pipeline stages of the device. Databus (TTL Compatible Input/Output Bus). Data, including color palette values and device control information is written to and read from the device over this 10-bit, bidirectional databus. 10-bit data or 8-bit data can be used. The databus can be configured for either 10-bit parallel data or byte data (8+2) as well as standard 8-bit data. Any unused bits of the databus should be terminated through a resistor to either he digital power plane (VCC) or GND. Chip Enable (TTL Compatible Input). This input must be at Logic "0" when writing to or reading from the device over the databus (D0-D9). Internally, data is latched on the rising edge of CE.
SCKOUT
CLOCK, CLOCK
BLANK SYNC
SYNCOUT D0-D9
CE
-8-
REV. B
ADV7152
Mnemonic R/W Function Read/Write Control (TTL Compatible Input). This input determines whether data is written to or read from the device's registers and color palette RAM. R/W and CE must be at Logic "0" to write data to the part. R/W must be at Logic "1" and CE at Logic "0" to read from the device. Command Controls (TTL Compatible Inputs). These inputs determine the type of read or write operation being performed on the device over the databus (see Interface Truth Table). Data on these inputs is latched on the falling edge of CE. Red, Green and Blue Current Outputs (High Impedance Current Sources). These RGB video outputs are specified to directly drive RS-343A and RS-170 video levels into doubly terminated 75 loads. IOR, IOG and IOB are the complementary outputs of IOR, IOG and IOB. These outputs can be tied to GND if it is not required to use differential outputs. VREF Voltage Reference Input (Analog Input). An external 1.235 V voltage reference is required to drive this input. An AD589 (2-terminal voltage reference) or equivalent is recommended. (Note: It is not recommended to use a resistor network to generate the voltage reference.) Output Full-Scale Adjust Control (Analog Input). A resistor connected between this pin and analog ground controls the absolute amplitude of the output video signal. The value of RSET is derived from the full-scale output current on IOG according to the following equations: RSET () = C1 x RREF/IOG (mA); SYNC on GREEN RSET () = C2 x RREF/IOG (mA); No SYNC on GREEN. Full-Scale output currents on IOR and IOB for a particular value of RSET are given by: IOR (mA)= C2 x RREF(V)/RSET () and IOB (mA) = C2 x RREF (V)/RSET () where C1 = 6,050: PEDESTAL = 7.5 IRE where C1 = 5,723: PEDESTAL = 0 IRE and where C2 = 4,323: PEDESTAL = 7.5 IRE where C1 = 3,996: PEDESTAL = 0 IRE. COMP IPLL Compensation Pin. A 0.1 F capacitor should be connected between this pin and VAA. Phase Lock Loop Output Current (High Impedance Current Source). This output is used to enable multiple ADV7150/ADV7152s along with ADV7151s to be synchronized together with subpixel resolution when using an external PLL. This output is triggered either from the falling edge of SYNC or BLANK as determined by bit CR21 of Command Register 2. When activated, it supplies a current corresponding to IPLL (mA) = 1,728 x RREF(V)/RSET () When not using the IPLL function, this output pin should be tied to GND. VAA GND Power Supply (+5 V 5%). The part contains multiple power supply pins, all should be connected together to one common +5 V filtered analog power supply. Analog Ground. The part contains multiple ground pins, all should be connected together to the system's ground plane.
C0, C1
IOR; IOR, IOG; IOG, IOB; IOB
RSET
REV. B
-9-
ADV7152
(Continued from page 1) applications. The part is controlled and programmed through the microprocessor (MPU) port. The part also contains a number of onboard test registers, associated with self diagnostic testing of the device. The individual Red, Green and Blue pixel input ports allow True-Color, image rendition. True-Color image rendition, at speeds of up to 220 MHz, is achieved through the use of the onboard data multiplexer/serializer. The pixel input ports flexibility allows for direct interface to most standard frame buffer memory configurations. The 30 bits of resolution, associated with the color look-up table and triple 10-bit DAC, realizes 24-bit True-Color resolution, while also allowing for the onboard implementation of linearization algorithms, such as Gamma-Correction. This allows effective 30-bit True-Color operation. The on-chip video clock controller circuit generates all the internal clocking and some additional external clocking signals. An external ECL oscillator source with differential outputs is all that is required to drive the CLOCK and CLOCK inputs of the ADV7152. The part can also be driven by an external clock generator chip circuit, such as the AD730. The ADV7152 is capable of generating RGB video output signals which are compatible with RS-343A and RS-170 video standards, without requiring external buffering. Test diagnostic circuitry has been included to complement the users system level debugging. The ADV7152 is fabricated in a +5 V CMOS process. Its monolithic CMOS construction ensures greater functionality with low power dissipation. The ADV7152 is packaged in a plastic 100-pin power quad flatpack (QFP). Superior thermal dissipation is achieved by inclusion of a copper heatslug, within the standard package outline to which the die is attached.
CIRCUIT DETAILS AND OPERATION
OVERVIEW
Pixel Port and Clock Control Circuit
Digital video or pixel data is latched into the ADV7152 over the devices Pixel Port. This data acts as a pointer to the onboard Color Palette RAM. The data at the RAM address pointed to is latched into the digital-to-analog converters (DACs) and output as an RGB analog video signal. For the purposes of clarity of description, the ADV7152 is broken down into three separate functional blocks. These are: 1. Pixel port and clock control circuit 2. MPU port, registers and color palette 3. Digital-to-analog converters and video outputs Table I shows the architectural and packaging differences between other devices in the ADV715x series of workstation parts. (For more details consult the relevant data sheets.)
Table I. Architectural and Packaging Differences of the ADV715x Series
Description 24-Bit "Gamma" True Color 24-Bit "Standard" True Color 8-Bit "Gamma" Pseudo Color 8-Bit "Standard" Pseudo Color 15-Bit True Color 220 MHz - True Color 220 MHz - Pseudo Color Triple 10-Bit DACs 4:1 Multiplexing 2:1 Multiplexing 1:1 Multiplexing 160-Lead QFP 100-Lead QFP ADV7150* * * * * * * * * * * * * ADV7152 * * * * * * * * * * * ADV7151*
The Pixel Port of the ADV7152 is directly interfaced to the video/graphics pipeline of a computer graphics subsystem. It is connected directly or through a gate array to the video RAM of the systems Frame-Buffer (video memory). The pixel port on the device consists of: Color Data Pixel Controls Palette Selects Clock Inputs Clock Outputs RED, GREEN, BLUE SYNC, BLANK PS0-PS1 CLOCK, CLOCK, LOADIN, SCKIN LOADOUT, PRGCKOUT, SCKOUT
The associated clocking signals for the pixel port include:
These onboard clock control signals are included to simplify interfacing between the part and the frame buffer. Only two control input signals are necessary to get the part operational, CLOCK and CLOCK (ECL Levels). No additional signals or external glue logic are required to get the Pixel Port & Clock Control Circuit of the part operational.
Pixel Port (Color Data)
* *
* * * * * *
The ADV7152 has 48 color data inputs. The part has two (for 2:1 multiplexing) 24-bit wide direct color data inputs. These are user programmed to support a number of color data formats including 24-Bit True Color, 15-Bit True Color and 8-Bit Pseudo Color (see "Color Data Formats" section) in 2:1 and 1:1 multiplex modes.
RED
8
A
24 24
GREEN 8 BLUE 8 B 24 MULTIPLEXER
*See ADV7151 and ADV7150 data sheets for more information on these parts.
Figure 10. Multiplexed Color Inputs for the ADV7152
-10-
REV. B
ADV7152
Color data is latched into the parts pixel port on every rising edge of LOADIN (see Timing Waveform, Figure 3). The required frequency of LOADIN is determined by the multiplex rate, where fLOADIN = fCLOCK/2 fLOADIN = fCLOCK 2:1 Multiplex Mode 1:1 Multiplex Mode resultant pixel or dot clock rate of 100 MHz. As mentioned in the previous section, the ADV7152 supports a number of color data formats in 2:1 and 1:1 multiplex modes. In 1:1 multiplex mode, the ADV7152 is clocked using the LOADIN signal. This means that there is no requirement for differential ECL inputs on CLOCK and CLOCK. The pixel clock is connected directly to LOADIN. (Note: The ECL CLOCK can still be used to generate LOADOUT PRGCKOUT, etc.)
VIDEO MEMORY/ FRAME BUFFER
24 VRAM (BANK A) 50MHz
Other pixel data signals latched into the device by LOADIN include SYNC, BLANK and PS0-PS1. Internally, data is pipelined through the part by the differential pixel clock inputs, CLOCK and CLOCK. The LOADIN control signal needs only have a frequency synchronous relationship to the pixel CLOCK (see "Pipeline Delay & Onboard Calibration" section). A completely phase independent LOADIN signal can be used with the ADV7152, allowing the CLOCK to occur anywhere during the LOADIN cycle. Alternatively, the LOADOUT signal of the ADV7152 can be used. LOADOUT can be connected either directly or indirectly to LOADIN. Its frequency is automatically set to the correct LOADIN requirement.
SYNC, BLANK
ADV7152
A
MULTIPLEXER 24 100MHz (2 x 50MHz)
24 VRAM (BANK B) 50MHz
B
The BLANK and SYNC video control signals drive the analog outputs to the blanking and SYNC levels respectively. These signals are latched into the part on the rising edge of LOADIN. The SYNC information is encoded onto the IOG analog signal when bit CR22 of Command Register 2 is set to a Logic "1." The SYNC input is ignored if CR22 is set to "0."
SYNCOUT
Figure 11. Direct Interfacing of Video Memory to ADV7152
CLOCK CONTROL CIRCUIT
In some applications where it is not permissible to encode SYNC on green (IOG), SYNCOUT can be used as a separate TTL digital SYNC output. This has the advantage over an independent (of the ADV7150) SYNC in that it does not necessitate knowing the absolute pipeline delay of the part. This allows complete independence between LOADIN/Pixel Data and CLOCK. The SYNC input is connected to the device as normal with Bit CR22 of Command Register 2 set to "0" thereby preventing SYNC from being encoded onto IOG. Bit CR12 of Command Register 1 is set to "1," enabling SYNCOUT. The output signal generates a TTL SYNCOUT with correct pipeline delay that is capable of directly driving the composite SYNC signal of a computer monitor.
PS0-PS1 (Palette Priority Select Inputs)
The ADV7152 has an integrated Clock Control Circuit (Figure 12). This circuit is capable of both generating the ADV7152's internal clocking signals as well as external graphics subsystem clocking signals. Total system synchronization can be attained by using the parts output clocking signals to drive the controlling graphics processor's master clock as well as the video frame buffers shift clock signals.
CLOCK, CLOCK Inputs
The Clock Control Circuit is driven by the pixel clock inputs, CLOCK and CLOCK. These inputs can be driven by a differential ECL oscillator running from a +5 V supply.
CLOCK CLOCK ECL TO TTL
PRGCKOUT
DIVIDE BY N (/ N)
DIVIDE BY M (/ M)
These pixel port select inputs determine whether or not the device is selected. These controls effectively determine whether the devices RGB analog outputs are turned-on or shut down. When the analog outputs are shut down, IOR, IOG and IOB are forced to 0 mA regardless of the state of the pixel and control data inputs. This state is determined on a pixel by pixel basis as the PS0-PS1 inputs are multiplexed in exactly the same format as the pixel port color data. These controls allow for switching between multiple palette devices (see Appendix 4). If the values of PS0 and PSI match the values programmed into bits MR16 and MR17 of the Mode Register, then the device is selected, if there is no match the device is effectively shut down.
Multiplexing
LOADOUT
SCKOUT LATCH BLANK SYNC SCKIN
ENABLE
LOADIN
ADV7152
TO COLOR DATA MULTIPLEXER
The onboard multiplexers of the ADV7152 eliminate the need for external data serializer circuits. Multiple video memory devices can be connected, in parallel, directly to the device. Figure 11 shows two memory banks of 50 MHz memory connected to the ADV7152, running in 2:1 multiplex mode, giving a REV. B -11-
M IS A FUNCTION OF MULTIPLEX RATE M = 2 IN 2:1 MULTIPLEX MODE M = 1 IN 1:1 MULTIPLEX MODE
N IS INDEPENDENTLY PROGRAMMABLE N= (4, 8, 16, 32)
Figure 12. Clock Control Circuit of the ADV7152
ADV7152
Alternatively, the ADV7152 CLOCK inputs can be driven by a Programmable Clock Generator (Figure 13), such as the ICS1562. The ICS1562 is a monolithic, phase-locked-loop, clock generator chip. It is capable of synthesizing differential ECL output frequencies in a range up to 220 MHz from a single low frequency reference crystal.
LOW FREQUENCY OSCILLATOR GND VCC 220 ECL OUT+ +5V ECL OUT- 330 330 GND VCC +5V VCLOCK 220 CLOCK CLOCK VAA
If it is not necessary to have a known fixed number of pipeline delays, then there is no limitation on the delay between LOADOUT and LOADIN (LOADOUT(1) and LOADOUT(2)). LOADIN and Pixel Data must conform to the setup and hold times (t8 and t9). If however, it is required that the ADV7152 has a fixed number of pipeline delays (tPD), LOADOUT and LOADIN must conform to timing specifications t10 and -t11 as illustrated in Figures 4 and 5.
PRGCKOUT
The PRGCKOUT control signal outputs a user programmable clock frequency. It is a divided down frequency of the pixel CLOCK (see Figure 8). The rising edge of PRGCKOUT is synchronous to the rising edge of LOADOUT
fPRGCKOUT = f CLOCK/N
CLOCK GENERATOR
GND
VAA
ADV7152
where N = 4, 8, 16 or 32. One application of the PRGCKOUT is to use it as the master clock frequency of the graphics subsystems processor or controller.
SCKIN, SCKOUT
0.1 F VREF OUT VREF
GND D0-D3 CS R/W
GND
Figure 13. PLL Generator Driving CLOCK, CLOCK of the ADV7152
CLOCK CONTROL SIGNALS LOADOUT
These video memory signals are used to minimize external support chips. Figure 15 illustrates the function that is provided. An input signal applied to SCKIN is synchronously AND-ed with the video blanking signal (BLANK). The resulting signal is output on SCKOUT. Figure 7 of the Timing Waveform section shows the relationship between SCKOUT, SCKIN and BLANK.
SCKOUT LATCH BLANK SYNC SCKIN
ENABLE
The ADV7152 generates a LOADOUT control signal which runs at a divided down frequency of the pixel CLOCK. The frequency is automatically set to the programmed multiplex rate, controlled by CR36 of Command Register 3. fLOADOUT = fCLOCK/2 fLOADOUT = fCLOCK 2:1 Multiplex Mode 1:1 Multiplex Mode
The LOADOUT signal is used to directly drive the LOADIN pixel latch signal of the ADV7152. This is most simply achieved by tying the LOADOUT and LOADIN pins together. Alternatively, the LOADOUT signal can be used to drive the frame buffer's shift clock signals, returning to the LOADIN input delayed with respect to LOADOUT.
LOADOUT(1) LOADOUT VIDEO FRAME BUFFER LOADOUT VIDEO FRAME BUFFER LOADOUT(2)
Figure 15. SCKOUT Generation Circuit
The SCKOUT signal is essentially the video memory shift control signal. It is stopped during the screen retrace. Figure 16 shows a suggested frame buffer to ADV7152 interface. This is a minimum chip solution and allows the ADV7152 control the overall graphics system clocking and synchronization.
LOADOUT LOADIN SCKIN
ADV7152
LOADIN PIXEL DATA
ADV7152
LOADIN PIXEL DATA
VIDEO FRAME BUFFER
ADV7152
BLANK SCKOUT
LOADOUT
LOADOUT(1)
DELAY
PIXEL DATA
LOADIN
LOADOUT(2)
Figure 16. ADV7152 Interface Using SCKIN and SCKOUT Figure 14. LOADOUT vs. Pixel Clock Input (CLOCK, CLOCK)
-12-
REV. B
ADV7152
Pipeline Delay and On-Board Calibration
The ADV7152 has a fixed number of pipeline delays (tPD), so long as timings t10 and -t11 are met. However, if a fixed pipeline delay is not a requirement, timings t10 and -t11 can be ignored, a calibration cycle must be run and there is no restriction on LOADIN to LOADOUT timing. If timings t10 and -t11 are not met, the part will function correctly though with an increased number of pipeline delays, tPD + N CLOCKS (for 2:1 mode N = 2, for 1:1 mode N = 0). The ADV7152 has onboard calibration circuitry which synchronizes pixel data and LOADIN with the internal ADV7152 clocking signals. Calibration can be performed in two ways: during the devices initialization sequence by toggling two bits of the Mode Register, MR10 followed by MR15, or by writing a "1" to Bit CR10 of Command Register 1 which executes a calibration on every Vertical Sync.
COLOR VIDEO MODES
24-BIT PIXEL DATA
24-BIT TO 24-BIT LOOK-UP-TABLE
24-BIT COLOR DATA
ANALOG VIDEO OUTPUTS
8
RED 256 x 8 GREEN 256 x 8 BLUE 256 x 8
8
8-BIT RED DAC 8-BIT GREEN DAC 8-BIT BLUE DAC
RED OUT GREEN OUT BLUE OUT
8
8
8
8
Figure 18. 24-Bit to 24-Bit Direct True-Color Configuration
8-Bit "Gamma" Pseudo Color (CR25, CR26, CR27 = X, 0, 0 or X, 1, 0 or X, 0, 1 and MR11 = 1)
The ADV7152 supports a number of color video modes all at the maximum video rate. Command bits CR24-CR27 of Command Register 2 along with Bit MR11 of Mode Register 1 determine the color mode.
24-Bit "Gamma" True Color (CR25, CR26, CR27 = 1, 1, 1 and MR11 = 1)
This mode sets the part into 8-bit Pseudo-Color operation. The pixel port accepts 8 bits of pixel data which indexes a 30-bit word in the Look-Up Table RAM. The Look-Up Table is configured as a 256 location by 30 bits deep RAM (10 bits each for Red, Green and Blue). The output of the RAM drives the DACs with 30-bit data (10 bits each for Red, Green and Blue).
8-BIT PIXEL DATA 8-BIT TO 30-BIT LOOK-UP-TABLE 30-BIT COLOR DATA ANALOG VIDEO OUTPUTS
The part is set to 24-bit/30-bit True-Color operation. The pixel port accepts 24 bits of color data which is directly mapped to the Look-Up Table RAM. The Look-Up Table is configured as a 256 location by 30 bits deep RAM (10 bits each for Red, Green and Blue). The output of the RAM drives the DACs with 30-bit data (10 bits each for Red, Green and Blue). The RAM is preloaded with a user determined, nonlinear function, such as a gamma correction curve.
24-BIT PIXEL DATA 24-BIT TO 30-BIT LOOK-UP-TABLE 30-BIT COLOR DATA ANALOG VIDEO OUTPUTS
8
RED 256 x 10 GREEN 256 x 10 BLUE 256 x 10
10
10-BIT RED DAC 10-BIT GREEN DAC 10-BIT BLUE DAC
RED OUT GREEN OUT BLUE OUT
10
10
Figure 19. 8-Bit to 30-Bit Pseudo-Color Configuration
8 RED 256 x 10 GREEN 256 x 10 BLUE 256 x 10 10 10-BIT RED DAC 10-BIT GREEN DAC 10-BIT BLUE DAC RED OUT GREEN OUT BLUE OUT
This mode allows for the display of 256 simultaneous colors out of a total palette of millions of addressable colors.
8-Bit "Standard" Pseudo Color (CR25, CR26, CR27 = X, 0, 0 or X, 1, 0 or X, 0, 1 and MR11 = 0)
8
10
8
10
Figure 17. 24-Bit to 30-Bit True-Color Configuration
This mode allows for the display of full 24-bit, GammaCorrected True-Color Images.
24-Bit "Standard" True Color (CR25, CR26, CR27 = 1, 1, 1 and MR11 = 0)
This mode sets the part into 8-bit Pseudo-Color operation. The pixel port accepts 8 bits of pixel data which indexes a 24-bit word in the Look-Up Table RAM. The Look-Up Table is configured as a 256 location by 24 bits deep RAM (10 bits each for Red, Green and Blue). The output of the RAM drives the DACs with 24-bit data (8 bits each for Red, Green and Blue).
8-BIT PIXEL DATA 8-BIT TO 24-BIT LOOK-UP-TABLE 24-BIT COLOR DATA ANALOG VIDEO OUTPUTS
This mode sets the part into direct 24-bit True-Color operation. The pixel port accepts 24 bits of color data which is directly mapped to Look-Up Table RAM. The Look-Up Table is configured as a 256 location by 24 bits deep RAM (8 bits each for Red, Green and Blue) and essentially acts as a bypass RAM. The output of the RAM drives the DACs with 24-bit data (8 bits each for Red, Green and Blue). The RAM is preloaded with a linear function. This mode allows for the display of full 24-bit True-Color Images.
8
RED 256 x 8 GREEN 256 x 8 BLUE 256 x 8
8
8-BIT RED DAC 8-BIT GREEN DAC 8-BIT BLUE DAC
RED OUT GREEN OUT BLUE OUT
8
8
Figure 20. 8-Bit to 24-Bit Pseudo-Color Configuration
REV. B
-13-
ADV7152
This mode allows for the display of 256 simultaneous colors out of a total palette of millions of addressable colors.
15-Bit "Gamma" True Color (CR24, CR25, CR26, CR27 = 0, 0, 1, 1 or 1, 0, 1, 1 and MR11 = 1) PIXEL PORT MAPPING
The pixel data to the ADV7152 is automatically mapped in the parts pixel port as determined by the pixel data mode programmed (Bits CR24-CR27 of Command Register 2). Pixel data in the 24-bit True-Color modes is directly mapped to the 24 color inputs R0-R7, G0-G7 and B0-B7.
R4 R3 R2 R1 R0 x x x
The part is set to 15-bit True-Color operation. The pixel port accepts 15 bits of color data which is mapped to the 5 LSBs of each of the red, green and blue palettes of the Look-Up Table RAM. The Look-Up Table is configured as a 32 location by 30 bits deep RAM (10 bits each for Red, Green and Blue). The output of the RAM drives the DACs with 30-bit data (10 bits each for Red, Green and Blue).
15-BIT PIXEL DATA 15-BIT TO 30-BIT LOOK-UP-TABLE 30-BIT COLOR DATA ANALOG VIDEO OUTPUTS
R7 R6 R5 R4 R3 R2 R1 R0
R4 R3 R2 R1 R0 x x x
0 0 0 R4 R3 5 R2 R1 R0
LOCATION "0" LOCATION "31"
256 x 10 RAM (RED LUT)
10
5
RED 32 x 10 GREEN 32 x 10 BLUE 32 x 10
10
TO RED DAC
10-BIT RED DAC 10-BIT GREEN DAC 10-BIT BLUE DAC
RED OUT
G4
G7 G6 G5 G4 G3 G2 G1 G0
G4 G3 G2 G1 G0 x x x
0 0 0 G4 G3 5 G2 G1 G0
LOCATION "0" LOCATION "31"
5
10
GREEN OUT BLUE OUT
G3 G2 G1 G0 x x
256 x 10 RAM (GREEN LUT)
5
10
10 TO GREEN DAC
Figure 21. 15-Bit to 30-Bit True-Color Configuration
x
This mode allows for the display of 15-bit, Gamma-Corrected True-Color Images.
15-Bit "Standard" True Color (CR24, CR25, CR26, CR27 = 0, 0, 1, 1 or 1, 0, 1, 1 and MR11 = 0)
B4 B3 B2 B1 B0 x x x PIXEL INPUT DATA
B7 B6 B5 B4 B3 B2 B1 B0
B4 B3 B2 B1 B0 x x x DATA LATCHED TO PIXEL PORT
0 0 0 B4 B3 5 B2 B1 B0 DATA INTERNALLY SHIFTED TO 5 LSBS
LOCATION "0" LOCATION "31"
256 x 10 RAM (BLUE LUT)
The part is set to 15-bit True-Color operation. The pixel port accepts 15 bits of color data which is mapped to the 5 LSBs of each of the red, green and blue palettes of the Look-Up Table RAM. The Look-Up Table is configured as a 32 location by 24 bits deep RAM (8 bits each for Red, Green and Blue). The output of the RAM drives the DACs with 24-bit data (8 bits each for Red, Green and Blue).
15-BIT PIXEL DATA 15-BIT TO 24-BIT LOOK-UP TABLE 24-BIT COLOR DATA ANALOG VIDEO OUTPUTS
10
TO BLUE DAC
PIN ASSIGNMENTS
DATA LATCHES FIRST 32 LOCATIONS OF RAM
Figure 23. 15-Bit True-Color Mapping Using R3-R7, G3-G7 and B3-B7
5
RED 32 x 8 GREEN 32 x 8 BLUE 32 x 8
8
8-BIT RED DAC 8-BIT GREEN DAC 8-BIT BLUE DAC
RED OUT GREEN OUT BLUE OUT
5
8
There are three modes of operation for 8-bit Pseudo Color. Each mode maps the input pixel data differently. Data can be input one of the three color channels, R0-R7 or G0-G7 or B0-B7. The part has two modes of operation for 15-bit True Color. In the first mode, data is input to the device over the red, green and blue channel (R3-R7, G3-G7 and B3-B7) and is internally mapped to locations 0 to 31 of the Look-Up Table (LUT) according to Figure 23. In the second mode, data is input to the device over just two of the color ports, red and green (R0-R7 and G0-G6) and is internally mapped to LUT locations 0 to 31 according to Figure 24. (Note: Data on unused pixel inputs is ignored.)
5
8
Figure 22. 15-Bit to 24-Bit True-Color Configuration
This mode allows for the display of 15-bit True-Color Images.
-14-
REV. B
ADV7152
R4 R3 R2 R1 R0 G4 G3 G2
R7 R6 R5 R4 R3 R2 R1 R0
R4 R3 R2 R1 R0 G4 G3 G2
0 0 0 R4 R3 5 R2 R1 R0
LOCATION "0" LOCATION "31"
Table II. Databus Width Table
256 x 10 RAM (RED LUT)
Databus Width
10
RAM/DAC Resolution 10 Bit 8 Bit 10 Bit 8 Bit
Read/Write Mode 10-Bit Parallel 8-Bit Parallel 8+2 Byte 8-Bit Parallel
TO RED DAC
10 Bit 10 Bit 8 Bit 8 Bit
Register Mapping
x G1 G0 B4 B3 B2 B1 B0
G7 G6 G5 G4 G3 G2 G1 G0
x G1 G0 B4 B3 B2 B1 B0
0 0 0 G4 G3 5 G2 G1 G0
LOCATION "0" LOCATION "31"
256 x 10 RAM (GREEN LUT)
10 TO GREEN DAC
The ADV7152 contains a number of onboard registers including the Mode Register (MR17-MR10), Address Register (A7- A0) and nine Control Registers as well as Red (R9-R0), Green (G9-G0) and Blue (B9-B0) Color Registers. These registers control the entire operation of the part. Figure 26 shows the internal register configuration. Control lines C1 and C0 determine which register the MPU is accessing. C1 and C0 also determine whether the Address Register is pointing to the color registers and look-up table RAM or the control registers. If C1, C0 = 1, 0, the MPU has access to whatever control register is pointed to by the Address Register (A7-A0). If C1, C0 = 0, 1, the MPU has access to the Look-Up Table RAM (Color Palette) through the associated color registers. The CE input latches data to or from the part. The R/W control input determines between read or write accesses. The Truth Tables III and IV show all modes of access to the various registers and color palette for both the 8-bit wide databus configuration and 10-bit wide databus configuration. It should be noted that after power-up, the devices MPU port is automatically set to 10-bit wide operation (see Power-On Reset section).
Color Palette Accesses
x x x x x x x x PIXEL INPUT DATA
B7 B6 B5 B4 B3 B2 B1 B0
x x x x x x x x DATA LATCHED TO PIXEL PORT
0 0 0 B4 B3 5 B2 B1 B0 DATA INTERNALLY SHIFTED TO 5 LSBS
LOCATION "0" LOCATION "31"
256 x 10 RAM (BLUE LUT)
10 TO BLUE DAC
PIN ASSIGNMENTS
DATA LATCHES FIRST 32 LOCATIONS OF RAM
Figure 24. 15-Bit True-Color Mapping Using R0-R7 and G0-G6
MICROPROCESSOR (MPU) PORT
The ADV7152 supports a standard MPU Interface. All the functions of the part are controlled via this MPU port. Direct access is gained to the Address Register, Mode Register and all the Control Registers as well as the Color Palette. The following sections describe the setup for reading and writing to all of the devices registers.
MPU Interface
The MPU interface (Figure 25) consists of a bidirectional, 10-bit wide databus and interface control signals CE, C0, C1 and R/W. The 10-bit wide databus is user configurable as illustrated.
CONTROL REGISTERS PIXEL MASK REGISTER ADDRESS REGISTER ADDR (A7-A0) MODE REGISTER (MR1) TEST REGISTERS ID REGISTER
Data is written to the color palette by first writing to the address register of the color palette location to be modified. The MPU performs three successive write cycles for each of the red, green and blue registers (10 bit or 8 bit). An internal pointer moves from red to green to blue after each write is completed. This pointer is reset to red after a blue write or whenever the address register is written. During the blue write cycle, the three bytes of red, green and blue are concatenated into a single 30-bit/24-bit word and written to the RAM location as specified in the address register (A7-A0). The address register then automatically increments to point to the next RAM location and a similar red, green and blue palette write sequence is performed. The address register resets to 00H following a blue write cycle to color palette RAM location FFH.
COMMAND REGISTERS (CR1-CR3) REVISION REGISTER
DATA TO PALETTES 30 RED REGISTER COLOR REGISTERS GREEN REGISTER BLUE REGISTER
MPU PORT 10 (8+2) CE R/W C0 C1 D0 - D9
Figure 25. MPU Port and Register Configuration
REV. B
-15-
ADV7152
Data is read from the color palette by first writing to the address register of the color palette location to be read. The MPU performs three successive read cycles from each of the red, green and blue locations (10-bit or 8-bit) of the RAM. An internal pointer moves from red to green to blue after each read is completed. This pointer is reset to red after a blue read or whenever the address register is written. The address register then automatically increments to point to the next RAM location, and a similar red, green and blue palette read sequence is performed. The address register resets to 00H following a blue read cycle of color palette RAM location FFH.
MODE REGISTER (MR17-MR10) ADDRESS REGISTER (A7-A0) C1 = 1 C0 = 0 ADDRESS REGISTER (A7-A0)
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH
Register Accesses
The MPU can write to or read from all of the ADV7152s registers. C0 and C1 determine whether the Mode Register or Address Register is being accessed. Access to these registers is direct. The Control Registers are accessed indirectly. The Address Register must point to the desired Control Register. Figure 28 along with the 8-bit and 10-bit Interface Truth Tables illustrate the structure and protocol for device communication over the MPU port.
C1 = 1 C0 = 1 C1 = 0 C0 = 0 C1 = 0 C0 = 1
CONTROL REGISTERS
PIXEL TEST REGISTER R G B DAC TEST REGISTER R G B SYNC, BLANK & I PLL TEST REGISTER ID REGISTER (READ ONLY) PIXEL MASK REGISTER COMMAND REGISTER 1 COMMAND REGISTER 2 COMMAND REGISTER 3 RESERVED* (READ ONLY) RESERVED* (READ ONLY) RESERVED* (READ ONLY) REVISION REGISTER POINTS TO LOCATION CORRESPONDING TO ADDRESS REG (A7-A0)
RED REGISTER (R9-R0)
GREEN REGISTER (G9-G0)
BLUE REGISTER (B9-B0)
LOOK-UP TABLE RAM (256 x 30)
ADDRESS REG = ADDRESS REG + 1
* THIS REGISTER IS READ ONLY.
Figure 26. Internal Register Configuration and Address Decoding
Table III. Interface Truth Table (10-Bit Databus Mode)
R/W 0 0 0 0 0 0
C1 1 0 1 0 0 0
C0 1 0 0 1 1 1
Databus (D9-D0) DB7-DB0 DB7-DB0 DB7-DB0 DB9-DB0 DB9-DB0 DB9-DB0
Operation
Result
Write to Mode Register DB7-DB0 MR17-MR10 Write to Address Register DB7-DB0 A7-A0 Write to Control Registers DB7-DB0 Control Register (Particular Control Register Determined by Address Register) Write to RED Register DB9-DB0 R9-R0 Write to GREEN Register DB9-DB0 G9-G0 Write to BLUE Register DB9-DB0 B9-B0 Write RGB Data to RAM Location Pointed to by Address Register (A7-A0) Address Register = Address Register + 1 Read Mode Register MR17-MR10 DB7-DB0 Read Address Register A7-A0 DB7-DB0 Read Control Registers Register Data DB7-DB0 (Particular Control Register Determined by Address Register) Read RED RAM Location R9-R0 DB9-DB0 Read GREEN RAM Location G9-G0 DB9-DB0 Read BLUE RAM Location B9-B0 DB9-DB0 (RAM Location Pointed to by Address Reg (A7-A0)) Address Register = Address Register + 1 REV. B
1 1 1 1 1 1
1 0 1 0 0 0
1 0 0 1 1 1
DB7-DB0 DB7-DB0 DB7-DB0 DB9-DB0 DB9-DB0 DB9-DB0
DB = Data Bit.
-16-
ADV7152
Table IV. Interface Truth Table (8-Bit Databus Mode)*
R/W 0 0 0 0 0 0 0 0 0
C1 1 0 1 0 0 0 0 0 0
C0 1 0 0 1 1 1 1 1 1
Databus (D9-D0) DB7-DB0 DB7-DB0 DB7-DB0 DB9-DB2 DB1-DB0 DB9-DB2 DB1-DB0 DB9-DB2 DB1-DB0
Operation
Result
Write to Mode Register DB7-DB0 MR17-MR10 Write to Address Register DB7-DB0 A7-A0 Write to Control Registers DB7-DB0 Control Registers (Particular Control Register Determined by Address Register (A7-A0)) Write to RED Register DB9-DB2 R9-R2 Write to RED Register DB1-DB0 R1-R0 Write to GREEN Register DB9-DB2 G9-G2 Write to GREEN Register DB1-DB0 G1-G0 Write to BLUE Register DB9-DB2 B9-B2 Write to BLUE Register DB1-DB0 B1-B0 Write RGB Data to RAM Location Pointed to by Address Register (A7-A0) Address Register = Address Register + 1 Read Mode Register MR17-MR10 DB7-DB0 Read Address Register A7-A0 DB7-DB0 Read Control Registers Register Data DB7-DB0 (Particular Control Register Determined by Address Register) Read RED RAM Location R9-R2 DB9-DB2 Read RED RAM Location R1-R0 DB1-DB0 Read GREEN RAM Location G9-G2 DB9-DB2 Read GREEN RAM Location G1-G0 DB1-DB0 Read BLUE RAM Location B9-B2 DB9-DB2 Read BLUE RAM Location B1-B0 DB1-DB0 (RAM Location Pointed to by Address Register (A7-A0)) Address Register = Address Register + 1
1 1 1 1 1 1 1 1 1
1 0 1 0 0 0 0 0 0
1 0 0 1 1 1 1 1 1
DB7-DB0 DB7-DB0 DB7-DB0 DB9-DB2 DB1-DB0 DB9-DB2 DB1-DB0 DB9-DB2 DB1-DB0
*Writing or reading 10-bit data (DB9-DB0) over an 8-bit databus (D7-D0) requires two write or two read cycles. :DB9-DB2 is mapped to D7-D0 on the first cycle. :DB1-DB0 is mapped to D1-D0 on the second cycle. DB = Data Bit.
Power-On Reset
The output clocking signals are also set during this reset period. PRGCKOUT = CLOCK/32 LOADOUT = CLOCK/2 The power-on reset is activated when VAA goes from 0 V to 5 V. This reset is active for 1 s. The ADV7152 should not be accessed during this reset period. The pixel clock should be applied at power-up.
On power-up of the ADV7152 executes a power-on reset operation. This initializes the pixel port such that the pixel sequence AB starts at A. The Mode Register (MR17-MR10), Command Register 2 (CR27-CR20) and Command Register 3 (CR37- CR30) have all bits set to a Logic "1." Command Register 1 (CR17-CR10) has all bits set to a Logic "0."
REV. B
-17-
ADV7152
REGISTER PROGRAMMING MPU Databus Width (MR12)
The following section describes each register, including Address Register, Mode Register and each of the nine Control Registers in terms of its configuration.
Address Register (A7-A0)
As illustrated in the previous tables, the C0 and C1 control inputs, in conjunction with this address register specify which control register, or color palette location is accessed by the MPU port. The address register is 8-bits wide and can be read from as well as written to. When writing to or reading from the color palette on a sequential basis, only the start address needs to be written. After a red, green and blue write sequence, the address register is automatically incremented.
MODE REGISTER MR1 (MR19-MR10)
This bit determines the width of the MPU port. It is configured as either a 10-bit wide (D9-D0) or 8-bit wide (D7-D0) bus. 10-bit data can be written to the device when configured in 8-bit wide mode. The 8 MSBs are first written on D7-D0, then the two LSBs are written over D1-D0. Bits D9-D8 are zeros in 8-bit mode.
Operational Mode Control (MR14-MR13)
When MR14 is "0" and MR13 is "1," the part operates in normal mode.
Calibrate LOADIN (MR15)
The mode register is a 10-bit wide register. However for programming purposes, it may be considered as an 8-bit wide register (MR18 and MR19 are both reserved). It is denoted as MR17-MR10 for simplification purposes. The diagram shows the various operations under the control of the mode register. This register can be read from as well written to. In read mode, if MR18 and MR19 are read back, they are both returned as zeros.
MODE REGISTER (MR17-MR10) BIT DESCRIPTION Reset Control (MR10)
This bit automatically calibrates the onboard LOADIN/ LOADOUT synchronization circuit. A "0" to "1" transition initiates calibration. This bit is set to "0" in normal operation. See "Pipeline Delay and Calibration" section. This bit must be run through this cycle during the initialization sequence.
Palette Select Match Bits Control (MR17-MR16)
These bits allow multiple palette devices to work together. When bits PSI and PS0 match MR17 and MR16 respectively, the device is selected. If these bits do not match, the device is not selected and the analog video outputs drive 0 mA, see "Palette Priority Select Inputs" section.
Control Registers
This bit is used to reset the pixel port sampling sequence. This ensures that the pixel sequence AB starts at A. It is reset by writing a "1" followed by a "0" followed by a "1." This bit must be run through this cycle during the initialization sequence.
RAM-DAC Resolution Control (MR11)
The ADV7152 has 9 control registers. To access each register, two write operations must be performed. The first write to the address register specifies which of the 9 registers is to be accessed. The second access determines the value written to that particular control register.
Pixel Test Register (Address Reg (A7-A0) = 00H)
When this is programmed with a "1," the RAM is 30 bits deep (10 bits each for red, green and blue) and each of the three DACs is configured for 10-bit resolution. When MR11 is programmed with a "0," the RAM is 24 bits deep (8 bits each for red, green and blue) and the DACs are configured for 8-bit resolution. The two LSBs of the 10-bit DACs are pulled down to zero in 8-bit RAM-DAC mode.
This register is used when the device is in test/diagnostic mode. It is a 24-bit (8 bits each for RED, GREEN and BLUE) wide read-only register which allows the MPU to read data on the pixel port, see "Test Diagnostic" section.
MR19
MR18
MR17
MR16
MR15 CALIBRATE LOADIN
MR14
MR13
MR12
MR11
MR10
RESERVED* PALETTE SELECT MATCH BITS CONTROL
MR16 MR17 PS0 PS1
MPU DATA BUS WIDTH
MR12 0 1 8-BIT (D7-D0) 10-BIT (D9-D0)
MR15
OPERATIONAL MODE CONTROL
MR14 MR13 0 0 1 1 0 1 0 1 RESERVED NORMAL OPERATION RESERVED RESERVED
RAM-DAC RESOLUTION CONTROL
MR11 0 1 8-BIT 10-BIT
RESET CONTROL
MR10
* THESE BITS ARE READ-ONLY RESERVED BITS.
A READ CYCLE WILL RETURN ZEROS "00."
Mode Register 1 (MR1) (MR19-MR10)
-18-
REV. B
ADV7152
DAC Test Register (Address Reg (A7-A0) = 01H) COMMAND REGISTER 1 (CR1) (Address Reg (A7-A0) = 05H)
This register is used when the device is in test/diagnostic mode. It is a 30-bit (10 bits each for RED, GREEN and BLUE) wide read-only register which allows MPU access to the DAC port, see "Test Diagnostic" section.
SYNC, BLANK and IPLL Test Register (Address Reg (A7-A0) = 02H)
This register contains a number of control bits as shown in the diagram. CR1 is a 10-bit wide register. However for programming purposes, it may be considered as an 8-bit wide register (CR18 to CR19 are reserved). The diagram below shows the various operations under the control of CR1. This register can be read from as well as written to. In write mode, "0" should be written to CR11 and CR13-CR17. In read mode, CR11 and CR13-CR19 are returned as zeros.
COMMAND REGISTER 1 BIT DESCRIPTION Calibration Control (CR10)
This register is used when the device is in test/diagnostic mode. It is a 3-bit wide (3 LSBs) read/write register which allows MPU access to these particular pixel control bits, see "Test Diagnostic" section.
ID Register (Address Reg (A7-A0) = 03H)
This is an 8-bit wide "Identification" read-only register. For the ADV7152 it will always return the hexadecimal value 8CH.
Pixel Mask Register (Address Reg (A7-A0) = 04H)
This bit automatically calibrates the onboard LOADIN/ LOADOUT synchronization circuit. MR15 of Mode Register MR1 must be set to "0."
SYNCOUT Control (CR12)
The contents of the pixel mask register are individually bit-wise logically AND-ed with the Red, Green and Blue pixel input stream of data. It is an 8-bit read/write register with D0 corresponding to R0, G0 and B0. For normal operation, this register is set with FFH.
This bit specified whether the video SYNCOUT signal is to be enabled. On power up a "0" is written to the bit and "SYNCOUT" is set three-state.
CR19
CR18
CR17
CR16
CR15
CR14
CR13
CR12
CR11
CR10
RESERVED * SYNCOUT CONTROL CR17-CR13 (00000) THESE BITS SHOULD BE SET TO ZERO CR12 0 1 DISABLE ENABLE SYNCOUT THIS BIT SHOULD BE SET TO ZERO CR11 (0)
CALIBRATION CONTROL
* THESE BITS ARE READ-ONLY RESERVED BITS.
A READ CYCLE WILL RETURN ZEROS "00."
CR10 0 1 DISABLE CALIBRATES ON EVERY VERTICAL SYNC (MR15=0)
Command Register 1 (CR1) (CR19-CR10)
REV. B
-19-
ADV7152
COMMAND REGISTER 2 (CR2) (Address Reg (A7-A0) = 06H) IPLL Trigger Control (CR21)
This register contains a number of control bits as shown in the diagram. CR2 is a 10-bit wide register. However for programming purposes, it may be considered as an 8-bit wide register (CR28 and CR29 are both reserved). The diagram shows the various operations under the control of CR2. This register can be read from as well written to. In read mode, CR28 and CR29 are both returned as zeros.
COMMAND REGISTER 2 BIT DESCRIPTION R7 Trigger Polarity Control (CR20)
This bit specifies whether the IPLL output is triggered from BLANK or SYNC.
SYNC Recognition Control (CR22)
This bit specifies whether the video SYNC input is to be encoded onto the IOG analog output or ignored.
Pedestal Enable Control (CR23)
This bit specifies whether a 0 IRE or a 7.5 IRE blanking pedestal is to be generated on the video outputs.
True-Color/Pseudo-Color Mode Control (CR27-CR24)
This bit determines whether the pixel data is latched into the test registers on the rising or falling edge of R7, see "Test Diagnostics" section in Appendix 3.
These 4 bits specify the various color modes. These include a 24-bit true-color mode, two 15-bit true-color modes and three 8-bit pseudo color modes.
CR29 CR28
CR27
CR26
CR25
CR24
CR23
CR22
CR21
CR20
RESERVED* * THESE BITS ARE READ-ONLY
RESERVED BITS. A READ CYCLE WILL RETURN ZEROS "00."
PEDESTAL ENABLE CONTROL
CR23 0 1 0 IRE 7.5 IRE
SYNC RECOGNITION CONTROL
CR22 0 1 IGNORE DECODE
TRUE-COLOR / PSEUDO-COLOR MODE CONTROL
CR27 CR26 CR25 CR24 0 0 1 1 1 1 0 1 0 1 1 1 0 0 0 0 0 1 0 0 0 0 1 0 COLOR MODE 8-BIT PSEUDO COLOR ON R7-R0 8-BIT PSEUDO COLOR ON G7-G0 8-BIT PSEUDO COLOR ON B7-B0 15-BIT TRUE COLOR ON R7-R3, G7-G3,B7-B3 15-BIT TRUE COLOR ON R7-R0, G6-G0 24-BIT TRUE COLOR R7-R0, G7-G0, B7-B0
IPLL TRIGGER CONTROL
CR21 0 1 SYNC BLANK
R7 TRIGGER POLARITY CONTROL
CR20 0 1
Command Register 2 (CR2) (CR29-CR20)
-20-
REV. B
ADV7152
COMMAND REGISTER 3 (CR3) (Address Reg (A7-A0) = 07H) BLANK Pipeline Delay Control (CR35-CR32)
This register contains a number of control bits as shown in the diagram. CR3 is a 10-bit wide register. However for programming purposes, it may be considered as an 8-bit wide register (CR38 and CR39 are both reserved). The diagram shows the various operations under the control of CR3. This register can be read from as well written to. In read mode, CR38 and CR39 are both returned as zeros.
COMMAND REGISTER 3-BIT DESCRIPTION PRGCKOUT Frequency Control (CR31-CR30)
These bits specify the additional pipeline delay that can be added to the BLANK function, relative to the overall device pipeline delay (tPD). As the BLANK control normally enters the video DAC from a shorter pipeline than the video pixel data, this control is useful in deskewing the pipeline differential.
Pixel Multiplex Control (CR36)
These bits specify the device's multiplex mode. It, therefore, also determines the frequency of the LOADOUT signal. LOADOUT is a divided down version of the pixel CLOCK.
Revision Register (Address Reg (A7-A0) = 0BH)
These bits specify the output frequency of the PRGCKOUT output. PRGCKOUT is a divided down version of the pixel CLOCK.
This register is a read only register containing the revision of silicon.
CR39
CR38
CR37
CR36
CR35
CR34
CR33
CR32
CR31
CR30
RESERVED* * THESE BITS ARE READ-ONLY
RESERVED BITS. A READ CYCLE WILL RETURN ZEROS "00".
EXTRA BLANK PIPELINE DELAY CONTROL (ADDS TO PIXEL PIPELINE DELAY; tPD )
CR35 CR34 CR33 CR32 0 0 0 - - 1 0 0 0 - - 1 0 0 1 - - 1 0 1 0 - - 1 BLANK PIPELINE DELAY
tPD tPD tPD
- -
tPD
+ 1 x LOADOUT + 2 x LOADOUT - - - - + 15 x LOADOUT
PIXEL MULTIPLEX CONTROL
CR37 CR36
PRGCKOUT FREQUENCY CONTROL
CR31 CR30
0 0 1 1
0 1 0 1
1:1 MUXING: LOADOUT = CLOCK /1 2:1 MUXING: LOADOUT = CLOCK /2 RESERVED RESERVED
0 0 1 1
0 1 0 1
CLOCK /4 CLOCK /8 CLOCK /16 CLOCK /32
Command Register 3 (CR3) (CR39-CR30)
REV. B
-21-
ADV7152
DIGITAL-TO-ANALOG CONVERTERS (DACS) AND VIDEO OUTPUTS
The ADV7152 contains three high speed video DACs. The DAC outputs are represented as the three primary analog color signals IOR (red video), IOG (green video) and IOB (blue video). Other analog signals on the part include IPLL and VREF as well as complementary video outputs IOR, IOG, IOB. These complementary outputs can be used to drive differentially terminated video loads, they will have equal but opposite output levels to IOR, IOG and IOB when loaded with a resistive load similar to IOR, IOG and IOB.
DACs and Analog Outputs
IOR, IOG, IOB DACs ZS =75
(SOURCE TERMINATION) (CABLE)
ZO = 75
ZL = 75
(MONITOR)
Figure 27. DAC Output Termination (Doubly Terminated 75 Load)
Reference Input and RSET
The part contains three matched 10-bit digital-to-analog converters. The DACs are designed using an advanced, high speed, segmented architecture. The bit currents corresponding to each digital input are routed to either IOR, IOG, IOB (bit = "1") or IOR, IOG, IOB (bit = "0"). (Normally IOR, IOG, IOB = GND.) The analog video outputs are high impedance current sources. Each of the these three RGB current outputs are specified to directly drive a 37.5 load (doubly terminated 75 ).
An external 1.23 V voltage reference is required to drive the analog outputs of the ADV7152. The reference voltage is connected to the VREF input. A resistor RSET is connected between the RSET input of the part and ground. For specified performance, RSET has a value of 280 . This corresponds to the generation of RS-343A video levels (with SYNC on IOG and Pedestal = 7.5 IRE) into a doubly terminated 75 load. Figure 28 illustrates the resulting video waveform, and the Video Output Truth Table shows the corresponding control input stimuli.
IOR, IOB mA 19.05 V 0.714 mA 26.67
IOG V 1.000 WHITE LEVEL
G
92.5 IRE
R
EY
SC
A
LE
1.44 0
0.054 0
9.05 7.62
0.340 7.5 IRE 0.286 40 IRE
BLACK LEVEL BLANK LEVEL
0
0
SYNC LEVEL
Figure 28. Composite Video Waveform (SYNC Decoded on IOG; Pedestal = 7.5 IRE; RSET = 280 )
Table V. Video Output Truth Table
Description WHITE LEVEL VIDEO VIDEO to BLANK BLACK LEVEL BLACK to BLANK BLANK LEVEL SYNC LEVEL
IOG (mA) 26.67 Video + 9.05 Video + 1.44 9.05 1.44 7.62 0
IOR, IOB (mA) 19.05 Video + 1.44 Video + 1.44 1.44 1.44 0 0
SYNC 1 1 0 1 0 1 0
BLANK 1 1 1 1 1 0 0
DAC Input Data 3FFH Data Data 000H 000H xxxH xxxH
-22-
REV. B
ADV7152
Variations on RS-343A
IOR, IOB, IOG mA V WHITE LEVEL 19.05 0.714
Various other video output configurations can be implemented by the ADV7152, including RS-170. Values of RSET for particular output video formats/levels are calculated by using the equations for RSET given in the "Pin Configuration" section. The table shows calculated values of RSET for some of the most common variants on the RS-343A standard. The associated waveforms are shown in the diagrams. RSET ( ) 265 280 259
IOR, IOB mA V IOG mA V WHITE LEVEL
100 IRE
Video Signal SYNC decoded on IOG; Pedestal = 0 IRE No SYNC decoded; Pedestal = 7.5 IRE No SYNC decoded; Pedestal = 0 IRE
0 0 BLACK/ BLANK LEVEL
Figure 31. Composite Video Waveform (Pedestal = 0 IRE; RSET = 259 )
IPLL Synchronization Output Control
18.62 0.698 26.67 1.000
GR EY
100 IRE
0
0
8.05
0.302 43 IRE
BLACK/BLANK LEVEL SYNC LEVEL
This output synchronization signal is used in applications where it is necessary to synchronize multiple palette devices (ADV7150 + ADV7151) to subpixel resolution. Each devices IPLL output signal is in phase with its analog RGB output signal. If multiple devices have differing output delays, the time difference can be derived from the IPLL signals. This time difference is then used to phase shift the CLOCK inputs on one or other of the devices inputs. The IPLL signal is internally triggered by either the falling edge of SYNC or BLANK as determined by CR21 of Command Register 2.
0
0
Figure 29. Composite Video Waveform (SYNC Decoded on IOG; Pedestal = 0 IRE; RSET = 265 )
IOR, IOB, IOG mA 19.05 V 0.714 WHITE LEVEL
92.5 IRE
GR EY
SC AL E
SC AL E
1.44 0
0.054 7.5 IRE 0
BLACK LEVEL BLANK LEVEL
Figure 30. Composite Video Waveform (Pedestal = 7.5 IRE; RSET = 280 )
REV. B
-23-
GR EY SC AL E
ADV7152
APPENDIX 1
BOARD DESIGN AND LAYOUT CONSIDERATIONS
The ADV7152 is a highly integrated circuit containing both precision analog and high speed digital circuitry. It has been designed to minimize interference effects on the integrity of the analog circuitry by the high speed digital circuitry. It is imperative that these same design and layout techniques be applied to the system level design such that high speed, accurate performance is achieved. The "Recommended Analog Circuit Layout" shows the analog interface between the device and monitor. The layout should be optimized for lowest noise on the ADV7152 power and ground lines by shielding the digital inputs and providing good decoupling. The lead length between groups of VAA and GND pins should by minimized so as to minimize inductive ringing.
Ground Planes
It is important to note that while the ADV7152 contains circuitry to reject power supply noise, this rejection decreases with frequency. If a high frequency switching power supply is used, the designer should pay close attention to reducing power supply noise and consider using a three terminal voltage regulator for supplying power to the analog power plane.
Digital Signal Interconnect
The digital inputs to the ADV7152 should be isolated as much as possible from the analog outputs and other analog circuitry. Also, these input signals should not overlay the analog power plane. Due to the high clock rates involved, long clock lines to the ADV7152 should be avoided to reduce noise pickup. Any active termination resistors for the digital inputs should be connected to the regular PCB power plane (VCC), and not the analog power plane.
Analog Signal Interconnect
The ground plane should encompass all ADV7152 ground pins, voltage reference circuitry, power supply bypass circuitry for the ADV7152, the analog output traces, and all the digital signal traces leading up to the ADV7152. The ground plane is the graphics board's common ground plane.
Power Planes
The ADV7152 and any associated analog circuitry should have its own power plane, referred to as the analog power plane (VAA). This power plane should be connected to the regular PCB power plane (VCC) at a single point through a ferrite bead. This bead should be located within three inches of the ADV7152. The PCB power plane should provide power to all digital logic on the PC board, and the analog power plane should provide power to all ADV7152 power pins and voltage reference circuitry. Plane-to-plane noise coupling can be reduced by ensuring that portions of the regular PCB power and ground planes do not overlay portions of the analog power plane, unless they can be arranged such that the plane-to-plane noise is common mode.
Supply Decoupling
The ADV7152 should be located as close as possible to the output connectors to minimize noise pick-up and reflections due to impedance mismatch. The video output signals should overlay the ground plane, and not the analog power plane, to maximize the high frequency power supply rejection. Digital Inputs, especially Pixel Data Inputs and clocking signals (CLOCK, LOADOUT, LOADIN, etc.) should never overlay any of the analog signal circuitry and should be kept as far away as possible. For best performance, the analog outputs (IOR, IOG, IOB) should each have a 75 load resistor connected to GND. These resistors should be placed as close as possible to the ADV7152 so as to minimize reflections. Normally, the differential analog outputs (IOR, IOG, IOB) are connected directly to GND. In some applications, improvements in performance are achieved by terminating these differential outputs with a resistive load similar in value to the video load. For a doubly terminated 75 load, this means that IOR, IOG, IOB are each terminated with 37.5 resistors.
For optimum performance, bypass capacitors should be installed using the shortest leads possible, consistent with reliable operation, to reduce the lead inductance. Best performance is obtained with 0.1 F ceramic capacitor decoupling. Each group of VAA pins on the ADV7152 must have at least one 0.1 F decoupling capacitor to GND. These capacitors should be placed as close as possible to the device.
-24-
REV. B
ADV7152
POWER SUPPLY DECOUPLING (0.1F AND 0.01F CAPACITOR FOR EACH V AA GROUP) 0.1F 0.01F 0.1F 0.01F 0.1F 0.01F 0.1F 0.01F
ANALOG POWER PLANE +5V (VAA ) 0.1F COMP VAA VREF RSET RSET 280 AD589 (1.2V REF) +5V (V AA ) 1k (1% METAL) 0.1F
+5V (VAA ) L1 (FERRITE BEAD)
+5V (VCC )
33F
0.1F
ADV7152
IOR
CO-AXIAL CABLE (75)
75 75
IOG 75 IOB 75 75 75 BNC CONNECTORS
MONITOR (CRT)
IOR IOG IOB IPLL COMPLIMENTARY OUTPUTS
GND
NOTES: 1. ALL RESISTORS ARE 1% METAL FILM 2. 0.1F AND 0.01F CAPACITORS ARE CERAMIC 3. ADDITIONAL DIGITAL CIRCUITRY OMITTED FOR CLARITY
Recommended Analog Circuit Layout
APPENDIX 2
TYPICAL FRAME BUFFER INTERFACE
CLOCK
CLOCK GENERATOR
CLOCK
ECL TO TTL DIVIDE BY N (/ N) DIVIDE BY M (+M)
PRGCKOUT LOADOUT
CLOCK
SCKOUT LATCH BLANK SYNC SCKIN
ENABLE
GRAPHICS PROCESSOR/ CONTROLLER
BLANK SYNC
LOADIN
ADV7152
24 24 TO PALETTE/RAM & DAC
24 VRAM (BANK A)
FRAME BUFFER/ VIDEO MEMORY
24 VRAM (BANK B)
24
MULTIPLEXER
REV. B
-25-
ADV7152
APPENDIX 3
10-BIT DACS AND GAMMA CORRECTION 10-Bit DACs Gamma Correction 8 Bits vs. 10 Bits
10-bit RAM-DAC resolution allows for nonlinear video correction, in particular Gamma Correction. The ADV7152 allows for an increase in color resolution from 24-bit to 30-bit effective color without the necessity of a 30-bit deep frame buffer. In true-color mode, for example, the part effectively operates as a 24-bit to 30-bit color look-up table. Up to now we have assumed that there exists a linear relationship between the actual RGB values input to a monitor and the intensity produced on the screen. This, however, is not the case. Half scale digital input (1000 0000) might correspond to only 20% output intensity on the CRT (Cathode Ray Tube). The intensity (ICRT) produced on a CRT by an input value IIN is given by: ICRT = (IIN) where ranges from 2.0 to 2.8. If the individual values of for red, green and blue are known, then so called "Gamma Correction" can be applied to each of the three video input signals (IIN); therefore: IIN(corrected) = k(IIN)1/ (k = 1, normally) Traditionally, there has been a tradeoff between implementing a nonlinear graphics function, such as gamma correction, and color dynamic range. The ADV7152 overcomes this by increasing the individual color resolution of each of the red, green and blue primary colors from 8 bits per color channel to 10 bits per channel (24 bits to 30 bits). The table highlights the loss of resolution when 8-bit data is gamma-corrected to a value of 2.7 and quantized in a traditional 8-bit system. Note that there is no change in the 8-bit quantized data for linear changes in the input data over much of the transfer function. On the other hand, when quantized to 10 bits via the 10-bit RAMs and 10-bit DACs of the ADV7152, all changes on the input 8-bit data are reflected in corresponding changes in the 10-bit data. The graph shows a typical gamma curve corresponding to a gamma value of 2.7. This is programmed to the red, green and blue RAMs of the color lookup table instead of the more traditional linear function. Different curves corresponding to any particular gamma value can be independently programmed to each of the red, green and blue RAMs. Other applications of the 10-bit RAM-DAC include closed-loop monitor color calibration.
8-Bit Data 240 241 242 243 244 245 246 247 248 249 250 251 252 253 254 255
1.00 0.90 0.80 0.70 0.60 0.50 0.40 0.30 0.20 0.10 0.00 0
Gamma Corrected (2.7) 0.977797 0.979304 0.980807 0.982306 0.983801 0.985292 0.986780 0.988264 0.989744 0.991220 0.992693 0.994161 0.995626 0.997088 0.998546 1.000000
Quantized to 8 Bits 250 250 251 251 25 1 252 252 252 253 253 254 254 254 255 255 255
Quantized to 10 Bits 1001 1002 1004 1005 1007 1008 1010 1011 1013 1015 1016 1018 1019 1021 1022 1023
VE UR NC IO CT E RE EY OR E AC TH MM Y B GA D VE EI EC PR E NS PO S RE R E EA IN NS L PO ES R T CR
DAC OUTPUT - Normalized to 1
32
64
96
128
160
192
224
256
INPUT CODE - Decimal
Gamma Correction Curve (Gamma Value = 2.7)
-26-
REV. B
ADV7152
APPENDIX 4
MULTIPLE PALETTE APPLICATIONS Palette Priority Select Inputs
The palette priority selection inputs allow up to four separate palette devices to be used in a single system to drive a single monitor. The IOR, IOG and IOB analog video output signals of each device are connected together, as shown. Signal inputs (PS0, PS1) determine on a pixel by pixel basis which palette device drives the monitor. This allows for implementation of multiple windows applications with each device acting as an independent palette. During initialization, each device is assigned two match bits, MR16 (PS0) and MR17 (PS1) in Mode Register MR1. PS0 and PS1 inputs will select one of the preprogrammed devices at any instant when PS0, PS1 matches MR16, MR17, respectively. When PS0 and PS1 do not match these bits, the DACs of the particular device are shut down, driving RGB outputs to 0 mA. PS0 and PS1 are multiplexed similar to the pixel data, thus allowing for subpixel resolution. The diagrams show an example of one ADV7152 operating in conjunction with three ADV7151's (Pseudo-Color RAM-DACs). Each displayed window on the monitor is driven by one of the four devices. Each device's analog output signals are connected together as shown.
Note: Only one palette device is selected at any particular instant. The analog output levels of the unselected devices will be 0 mA. Other applications for the palette priority function using a minimum of two devices (two ADV7152s or one ADV7152 and one ADV7151) include: Cursor Overlay on 24-Bit Graphics Active Live Video Overlay (from Frame Grabber) Text/Character Generation and Overlay
(DEVICE: 2)
IOR, IOG, IOB
DACs
(DEVICE: 1)
IOR, IOG, IOB
ZO =75
DACs
ZS = 75
(SOURCE TERMINATION) (CABLE)
ZL = 75 (MONITOR)
Multiple Devices Termination for a Single Monitor
ADV7152
R0-R7 G0-G7 B0-B7 256 x 30 RAM RGB ANALOG VIDEO
PALETTE SELECT BITS
PS0, PS1
MR16 MR17 0 0
ADV7151 (1)
256 x 30 PALETTE
PALETTE SELECT BITS
P0-P7
RGB ANALOG VIDEO
MONITOR
TRUE-COLOR BACKGROUND PS0 = 0: PS1 = 0 WINDOW 1 (Pseudo-Color) PS0 = 0: PS1 = 1 WINDOW 2 (Pseudo-Color) PS0 = 1: PS1 = 0
MR16 MR17 0 1 VIDEO TO MONITOR
ADV7151 (2)
256 x 30 PALETTE
PALETTE SELECT BITS
WINDOW 3 (Pseudo-Color) PS0 = 1: PS1 = 1
MR16 MR17 1 0
RGB ANALOG VIDEO
ADV7151 (3)
256 x 30 PALETTE
PALETTE SELECT BITS
MR16 MR17 1 1
RGB ANALOG VIDEO
Multiple Devices Driving a Multiwindow Application
REV. B
-27-
ADV7152
APPENDIX 5
INITIALIZATION AND PROGRAMMING
ADV7152 Initialization
After power has been supplied, the ADV7152 must be initialized. The Mode Register and Control Registers must be set. The values written to the various registers will be determined by the desired operating mode of the part, i.e., True Color/Pseudo Color, 2:1 Muxing/2:1 Muxing, etc.
Example 1
The following section gives examples of initialization of the ADV7152 operating in various modes.
Color Mode Multiplexing Databus RAM-DAC Resolution SYNC Pedestal
24-Bit True Color 2:1 8-Bit 8-Bit Enabled on IOG 7.5 IRE C1 1 1 1 1 1 0 1 0 1 0 1 0 1
C1
Register Initialization Write 09H to Mode Register (MR1) Write 08H to Mode Register (MR1) Write 09H to Mode Register (MR1) Write 29H to Mode Register (MR1) Write 09H to Mode Register (MR1) Write 04H to Address Register (A7-A0) Write FFH to Pixel Mask Register Write 05H to Address Register (A7-A0) Write 00H to Command Reg 1 (CR1) Write 06H to Address Register (A7-A0) Write ECH to Command Reg 2 (CR2) Write 07H to Address Register (A7-A0) Write 40H to Command Reg 3 (CR3)
Color Palette RAM Initialization
C0 1 1 1 1 1 0 0 0 0 0 0 0 0
C0
R/W 0 0 0 0 0 0 0 0 0 0 0 0 0
R/W
Comment Resets to Normal Operation, 8-Bit Bus/RAM-DAC *(Initializes Pipelining *( " *(Calibrates LOADOUT/LOADIN Timing *( " Address Reg Points to Pixel Mask Register Sets the Pixel Mask to All "1s" Address Reg Points to Command Register 1 (CR1) Address Reg Points to Command Register 2 (CR2) Sets 24-Bit Color, 7.5 IRE, SYNC on Green (IOG) Address Reg Points to Command Register 3 (CR3) Sets 2:1 Multiplexing, PRGCKOUT = CLOCK/4
Comment
Write Write Write Write Write Write Write * * Write Write Write
00H to Address Register (A7-A0) 00H (Red Data) to RAM Location (00H) 00H (Green Data) to RAM Location (00H) 00H (Blue Data) to RAM Location (00H) 01H (Red Data) to RAM Location (01H) 01H (Green Data) to RAM Location (01H) 01H (Blue Data) to RAM Location (01H) * * * * * * * * FFH (Red Data) to RAM Location (FFH) FFH (Green Data) to RAM Location (FFH) FFH (Blue Data) to RAM Location (FFH)
0 0 0 0 0 0 0 * * 0 0 0
0 1 1 1 1 1 1 * * 1 1 1
0 0 0 0 0 0 0 * * 0 0 0
Points to Color Palette RAM (Initializes Palette RAM ( to a Linear Ramp** ( ( ( ( ( ( ( ( (RAM Initialization Complete
**These four command lines reset the ADV7152. The pipelines for each of the Red, Creen and Blue pixel inputs are synchronously reset to the Multiplexer's "A" input. Mode Register bit MR10 is written by a "1" followed by "0" followed by "1." LOADIN/LOADOUT timing is internally synchronized by writing a "0" followed by a "1" followed by a "0" to Mode Register MR15. **This sequence of instructions would, of course, normally be coded using some form of loop instruction.
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REV. B
ADV7152
Example 2
Color Mode Multiplexing Databus RAM-DAC Resolution SYNC Pedestal Calibration
Register Initialization
24-Bit Gamma Corrected True Color (30 Bits) 2:1 10-Bit 10-Bit Ignored 0 IRE Every Vertical Sync
C1 C0 R/W Comment
Write Write Write Write Write Write Write Write Write Write Write Write Write
0FH to Mode Register (MR1) 0EH to Mode Register (MR1) 0FH to Mode Register (MR1) 2FH to Mode Register (MR1) 0FH to Mode Register (MR1) 04H to Address Register (A7-A0) FFH to Pixel Mask Register 05H to Address Register (A7-A0) 01H to Command Reg 1 (CR1) 06H to Address Register (A7-A0) E0H to Command Reg 2 (CR2) 07H to Address Register (A7-A0) 41H to Command Reg 3 (CR3)
1 1 1 1 1 0 1 0 0 0 1 0 1 C1 0 0 0 0 0 0 0 * * 0 0 0
1 1 1 1 1 0 0 0 0 0 0 0 0 C0 0 1 1 1 1 1 1 * * 1 1 1
0 0 0 0 0 0 0 0 0 0 0 0 0 R/W 0 0 0 0 0 0 0 * * 0 0 0
Resets to Normal Operation, 10-Bit Bus/RAM-DAC *(Initializes Pipelining *( " *(Calibrates LOADOUT/LOADIN Timing *( " Address Reg Points to Pixel Mask Register Sets the Pixel Mask to All "1s" Address Reg Points to Command Register 1 (CR1) Calibrates Every Vertical Sync Address Reg Points to Command Register 2 (CR2) Sets 24-Bit Color, 0 IRE, No SYNC Address Reg Points to Command Register 3 (CR3) Sets 2:1 Multiplexing, PRGCKOUT = CLOCK/8 Comment Points to Color Palette RAM (Initializes Palette RAM ( to a "Gamma" Ramp** ( ( ( ( ( ( ( ( (RAM Initialization Complete
Color Palette RAM Initialization Write 00H to Address Register (A7-A0) Write 000H (Red Data) to RAM Location (00H) Write 000H (Green Data) to RAM Location (00H) Write 000H (Blue Data) to RAM Location (00H) Write xxxH (Red Data) to RAM Location (01H) Write xxxH (Green Data) to RAM Location (01H) Write xxxH (Blue Data) to RAM Location (01H) * * * * * * * * * * Write 3FFH (Red Data) to RAM Location (FFH) Write 3FFH (Green Data) to RAM Location (FFH) Write 3FFH (Blue Data) to RAM Location (FFH)
**These four command lines reset the ADV7152 The pipelines for each of the Red, Green and Blue pixel inputs are synchronously reset to the Multiplexer's "A" input. Mode Register bit MR10 is written by a "1" followed by "0" followed by "1." LOADIN/LOADOUT timing is internally synchronized by writing a "0" followed by a "1" followed by a "0" to Mode Register MR15. **Data for a gamma curve characteristic is obtainable in Appendix 3.
REGISTER DIAGNOSTIC TESTING
The previous examples show the register initialization sequence for the ADV7152. These show control data going to the registers and palette RAM. As well as this writing function, it may also be necessary, due to system diagnostic requirements, to confirm that correct data has been transferred to each register and palette RAM location. There are two ways to incorporate register value/RAM value checking: 1. READ after each WRITE: After data is written to a particular register, it can be read back immediately. The following table shows an example with Command Registers CR2 and CR3.
C1 C0 R/W D0-D7 Comment
2. READ after all WRITEs completed: All registers and the color palette RAM are written to and set. Once this is complete, all registers are again accessed but this time in Read-Only mode. The table below shows this method for Command Registers CR2 and CR3.
C1 C0 R/W D0-D7 Comment
0 1 1 0 1 1
0 0 0 0 0 0
0 0 1 0 0 1
06H E0H E0H 07H 40H 40H
Select Command Register 2 (CR2) Sets 24-Bit True-Color Command Reg 2 Value Read-Back Select Command Register 3 (CR3) Set 2:1 Mux Mode Command Reg 3 Value Read-Back
0 1 0 1 0 1 0 1 1
0 0 0 0 0 0 0 0 0
0 0 0 0 0 1 0 1 1
06H E0H 07H 40H 06H E0H 07H 40H 40H
Select Command Register 2 (CR2) Sets 24-Bit True-Color Select Command Register 3 (CR3) Set 2:1 Mux Mode Select CR2 CR2 Value Read-Back Select CR3 CR3 Value Read-Back CR3 Value Read-Back
It is clear that this latter case requires more command lines than the previous READ after each WRITE case.
REV. B
-29-
ADV7152
APPENDIX 6
TEST DIAGNOSTICS
SYNC BLANK
PIXEL DATA
INPUT MUX
GRAPHICS PIPELINE
COLOR PALETTE RAM
GRAPHICS PIPELINE DACs
TRIGGER DECODE PIXEL TEST REGISTER COLOR REGISTERS
TRIGGER DECODE SYNC BLANK DAC TEST REGISTERS IPLL TEST REGISTER
MPU PORT
CE
R/W
C0
C1
D9-D0
Test/Diagnostic Block Diagram
The ADV7152 contains onboard circuitry which enables both device and system level test diagnostics. The test circuitry can be used to test the frame buffer memory as well as the functionality of the ADV7152. A number of test registers are integrated into the part which effectively allow for monitoring of the graphics pipeline. Pixel data is read from the graphics pipeline independent of the pixel CLOCK. The pixel data itself contains the triggering information that latches data into the test registers. This allows for system diagnostics in a continuously clocked graphics system. The test register data is then read by the microprocessor over the MPU. Access to the test registers is as described in the "Microprocessor (MPU) Port" section. This section also gives the address decode locations for the various test registers.
Test Trigger (R7)
the graphics pipeline and after a number of clocks get latched into the DAC Test Register. This data can then be read from the Pixel Test Register and the DAC Test Registers over the MPU Port. This data will remain in the Pixel Test Registers and the DAC Test Registers until the next rising edge of R7 causes new data to be latched in. In the above example, the next rising edge of R7 occurs on the Pixel n input. Therefore the data in the Pixel Test Registers and DAC Test Registers must be read over the MPU before the Pixel n data is applied, otherwise they will be overwritten by the Pixel n data and the Pixel 2 data will be lost.
Pixel Test Register
The test trigger is decoded from the pixel data stream. Bit R7 of the RED channel is assigned the task of latching pixel data into the test registers. A "0" to "1" or a "1" to "0" (as determined by bit CR20 of Command Register 2) transition on R7, fills the test register with the corresponding pixel data. This effectively means that a sequence of data travels along the graphics pipeline, with the test registers taking a sample only when there is a transition on Bit R7. The following example shows a sequence with the ADV7152 preset to sample the graphics pipeline on a low to high transition of R7. RED Pixel 0: Pixel 1: Pixel 2: Pixel 3: .... .... Pixel n-1: Pixel n: Pixel n: 00000000 0........ 1........ 0........ ... ... 0........ 1........ 0........ GREEN 00000000 ........ ........ ........ BLUE 00000000 ........ ........ ........
The read-only Pixel Test Register is 24 bits wide, 8 bits each for red, green and blue. It is situated directly after the Pixel Mask Register. After data is latched into this register by a transition on R7, it is read in three cycles over the MPU Port as described in the "Microprocessor (MPU) Port" section.
DAC Test Register
The DAC Test Register is latched with data some CLOCKs after the Pixel Test Register. The DAC Test Register is a 30-bit wide read-only register, corresponding to 10 bits each for red, green and blue data. It is located the Color Palette RAM. If the RAM-DAC is in 8-bit after resolution mode, the upper two bits of the red, green and blue data will be zero. After data is latched into the DAC Test Register by a transition on R7, it is read in three or six cycles over the MPU Port as described in the "Microprocessor (MPU) Port" section.
SYNC, BLANK and IPLL Test Register
........ ........ ........
........ ........ ........
This is an 8-bit wide register but with only three effective bits. The three lower bits correspond to SYNC, BLANK and IPLL respectively. The upper bits should be masked in software. This register is at the same position in the graphics pipeline as the DAC Test Register. When pixel data is latched into the DAC Test Register, the corresponding status of SYNC, BLANK and IPLL is latched into this register. It is read over the MPU Port as described in the "Microprocessor (MPU) Port" section. (Note: If BLANK is low, the corresponding pixel data to the DAC Test Register will be all "0s.") REV. B
In the above sequence of pixels, there is a rising edge on R7 on Pixel 2. The Red, Green and Blue data for Pixel 2, therefore, gets latched into the Pixel Test Register. Pixel 2 continues down
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ADV7152
APPENDIX 7
THERMAL AND ENVIRONMENTAL CONSIDERATIONS
The ADV7152 is a very highly integrated monolithic silicon device. This high level of integration, in such a small package, inevitably leads to consideration of thermal and environmental conditions in which the ADV7152 must operate. Reliability of the device is significantly enhanced by keeping it as cool as possible. In order to avoid destructive damage to the device, the absolute maximum junction temperature of 150C must never be exceeded. Certain applications, depending on pixel data rates, may require forced air cooling, or external heatsinks. The following data is intended as a guide in evaluating the operating conditions of a particular application so that optimum device and system performance is achieved. It should be noted that information on package characteristics published herein may not be the most up to date at the time of reading this. Advances in package compounds and manufacture will inevitably lead to improvements in the thermal data. Please contact your local sales office for the most up-to-date information.
Power Dissipation
Table A. Thermal Characteristics vs. Airflow
Air Velocity (Linear feet/min)
0 (Still Air)
50
100
200
JA (C/W) No Heatsink 35 EG&G D10100-28 Heatsink 32 Thermalloy 2290 Heatsink 25
Thermal Model
31 28 21
28 25 18
25 22 15
The junction temperature of the device in a specific application is given by: TJ = TA + PD (JC + CA) or TJ = TA + PD (JA) where: TJ = Junction Temperature of Silicon (C) TA = Ambient Temperature (C) PD = Power Dissipation (W) JC = Junction to Case Thermal Resistance (C/W) CA = Case to Ambient Thermal Resistance (C/W) JA = Junction to Ambient Thermal Resistance (C/W)
Package Enhancements
(1) (2)
The diagram shows graphs of power dissipation in watts vs. pixel clock frequency for the ADV7152.
1.50 VAA = +5V VREF = +1.2V POWER DISSIPATION - Watts TA = 25C 1.25
1.00
0.75
The standard QFP package has been enhanced to a PowerQuad2 package. This supports an improved thermal performance come pared to standard QFP. In this case, the die is attached to heatslug so that the power that is dissipated can be conducted to the external surface of the package. This provides a highly efficient path for the transfer of heat to the package surface. The package configuration also provides an efficient thermal path from the ADV7152 to the Printed Circuit Board via the leads.
Heatsinks
60 80 100 120 140 160 180 PIXEL CLOCK FREQUENCY - MHz 200 220
0.50
* THE "TYPICAL ON-SCREEN PATTERN" CORRESPONDS TO LINEAR CHANGES IN THE
PIXEL INPUT (I. E., A BLACK TO WHITE RAMP). IN GENERAL, COLOR IMAGES TEND TO APPROXIMATE THIS CHARACTERISTIC.
Typical Power Dissipation vs. Pixel Rate
Package Characteristics
The maximum silicon junction temperature should be limited to 100C. Temperatures greater than this will reduce long term device reliability. To ensure that the silicon junction temperature stays within prescribed limits, the addition of an external heatsink may be necessary. Heatsinks, will reduce JA as shown in the "Thermal Characteristics vs. Airflow" table.
The table of thermal characteristics shows typical information for the ADV7152 (100-Lead Plastic Power QFP) using various values of Airflow. Junction to Case (JC) Thermal Resistance for this particular part is:
JC (100-Lead Plastic Power QFP) = 1.0C/W
(Note: 0C is independent of airflow.)
REV. B
-31-
ADV7152
APPENDIX 8
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
0.952 (24.15) 0.932 (23.65) 0.792 (20.10) 0.784 (19.90) 80 81 51 50
0.715 (18.15) 0.696 (17.65) TOP VIEW 10 64 0.556 (14.10) 0.548 (13.90)
100 1 0.004 (0.102) MAX 44 MAX
PIN 1
31 30
0.014 (0.35) 0.011 (0.27) 0.134 (3.40) MAX 0.037 (0.95) 0.026 (0.65)
0.030 (0.75) 0.022 (0.55)
0.054 (1.37) 0.046 (1.17) 0.116 (2.94) 0.096 (2.44) 0.054 (1.37) 0.046 (1.17)
-32-
REV. B
PRINTED IN U.S.A.
C1695-10-8/94
100-Lead Plastic Power Quad Flatpack (S-100)

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